Tim Edwards Presentation on Efabless Raven RISC-V Based SoC


Tim Edwards, Senior Vice President of Analog and Platform, presented at the Free Silicon Conference on “The Raven Chip: First-time silicon success with qflow and efabless”. The Efabless Raven is unique among RISC-V offerings in the completeness of the open source solution – it is an open source top-level design built with a complete open source tool flow (offered on the Efabless platform). It incorporates a full suite of analog peripherals, offered from the X-FAB library at no cost, which can be added or removed to address a wide range of potential applications.

The Raven is silicon proven and is now offered in the Efabless marketplace as either silicon (with accompanying development boards) or as a template for community members to clone and redesign to meet their needs.

Tim’s presentation described (i) the Raven development process on the open source tool chain, (ii) the robustness of the open source flow delivering first time silicon success and (iii) the power of the Efabless platform to facilitate simple, protected access to tools and IP configured for a real foundry process.

The Raven was designed by the Efabless team, led by Tim Edwards and Mohamed Kassem, co-founder and CTO. The PicoRV32 RISC-V core was developed by Clifford Wolf. The Raven was built on the X-FAB XH180 process and incorporates various analog peripherals from the X-FAB library.