Imagine what your team could create if you could develop a custom analog/mixed signal chip for under $10K? Enter Efabless – for less than $10,000 we enable innovative people like you to realize their ideas in the form of a customized SoC. Our process is not only inexpensive but fast and straightforward. Open Innovation Hardware
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Using efabless Cloud V’s Symbiflow-based FPGA support
First, start by creating a new Cloud V workspace. We’ll start by creating a Pin Constraints File as shown: The following dialog will show up. Pick your desired FPGA family and board, and give the file a name. Pin-constraints file are, for your convenience, pre-populated! You don’t have to actually go in and add port
Part 2: Efabless & Arm Enable Fast Affordable Custom SoC Development
Efabless is committed to simplifying the process of smart product creation and making it available to everyone. The world is quickly advancing towards a trillion connected devices and in the process, forces are driving application developers towards creating custom silicon in order to attain or maintain their competitive advantage. Those forces include the need to:
Efabless & Arm Enable Fast Affordable Custom SoC Development
We are now in an exciting time where the realization of custom SoCs is cost-effective and affordable for small companies or low-volume projects. Those unfamiliar with custom chip design may find it daunting to move away from the world of off-the-shelf components but the benefits abound and are well within reach. In this short article
Air Force Microelectronics Challenge – an IC innovation first
I guess advanced semiconductor design really is for everyone! The Advanced Microelectronics Design and Prototype Challenge sponsored by the Air Force Research Labs and its innovation-enabling affiliate, AFWERX, is calling into question a major piece of semiconductor conventional wisdom – that advanced node IC design cost and a risk-averse US venture capital industry have killed
Webinar: How to design a RISC-V SoC
Now that we have covered major components of chip design through our online platform, we think this is the right time to move from “chip designing” to “chip planning” Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO
2017 Year in Review
It has been an exciting year for efabless and our community members. In 2017 we have made significant strides toward our vision, we introduced: First marketplace IP delivered via a design challenge. First customer-defined designs using Configurable Mixed Signal IC’s. First open ASIC design and sharing platform, Chiplicity. First open source RISC-V based reference SoC
X-FAB Sponsored Design Challenge is in the Books
Our first customer sponsored design challenge is in the books! It was a lot of hard work by the efabless team and by all of you. It was also a big success. Before I go any further, I want to say a few thank you’s. X-FAB took the important first step and sponsored the challenge
Datasheet and Testbench Updates for X-FAB Design Challenge
With the challenge underway, a few of the participants have identified a few errors and inconsistencies in the challenge spec sheet and characterization, which this update corrects. The changes included in this update are described below. We want to thank all of the participants who have identified issues and brought them to our attention. The
X-FAB Design Challenge – Update #1
Hello efabless community Its been a busy week at efabless. We are very excited to see the community involvement and because this is our first challenge we are sending the update to all our community members. We currently have more than 40 active solvers participating in the challenge. If you need any help, we are
Webinar : Design Challenge
Please join us on December 1 2016 at 8:00 AM PST for a webinar on the previously announced “Open Mixed Signal Design Challenge”. We will give a brief overview of the challenge and demonstrate how to use the online platform to design the ultra low power voltage reference. We will be happy to answer any questions you may have and
efabless Unveils Online Community to Reimagine Chip Design
Open Mixed Signal Design Challenge efabless corporation and X-FAB Silicon Foundries today announced the launch of an open mixed-signal design challenge. This challenge gives designers across the globe, of all levels of experience, the opportunity to deliver a completed design for an ultra-low power voltage reference IP. The design challenge emphasizes design creativity and execution quality to meet
